Transceiver System Hardware Composition

Each high-speed transceiver includes two channels, a transmitter and a receiver. The transmitter and receiver are composed of a physical coding sublayer (PCS, p-field si-cal coding sublayer) and a physical medium additional sublayer (PMA, physi-cal). media additional sublayer) consists of two parts.

PCS includes hard-core logic implementation of digital functions in transceivers compatible with supported protocols, transmit channels include phase compensation FIFO, byte serializer, 8B/10B encoder and other modules; receive channels include word aligner, rate matching FIFO , 8B/10B decoder, byte deserializer, byte sequencer, phase compensation FIFO and other modules.

The PMA includes analog circuitry for I/O buffers, CDR, serializer/deserializer (SER/DES), and programmable pre-emphasis and equalization to optimize serial data path performance.

When the device transceiver channel is working, the output parallel data in the FPGA architecture is transmitted through the transmitter PCS and PMA, and finally converted into serial data and sent out. The received input serial data is transmitted to the FP in a serial data format through the processing of the receiver PMA and PCS to carry out the next step of processing.